Design of a Parameterized Floating Point Multiplier
Xu Chen · Information and Electronic Engineering · 2006
Parameterized IP of floating point multiplier design method based on Verilog HDL is discussed in this paper,and three kinds of parameters are picked out.A new design method of multiplication operation between two fractions is pointed out,radix 4 Booth algorithm is used to compress partial products and a hybrid structure is used to divide partial products into several parts for parallel computing.The results are outputted by a carrying leading adder.As a parameterized design example,a single precision floating point multiplier module is given,which is provided with four grades of pipeline and a clock enabling port,and is compatible with IEEE754 as well.The experimental result indicates that the Parameterized Floating Point Multiplier IP core is reconfigurable and reusable.