FPGA Verification for a Kind of Complicated Chip
Xiaobo Li, Heng Zhang · Jisuanji gongcheng · 2006
This paper introduces a module hierarchy construction algorithm and an improved K-L algorithm which efficiently reduce the number of the interconnect signals during the partition of the design.It employs the CPM(certify pin multiple)method to solve the insufficiency of pins caused by the too many interconnections between several FPGAs.On the other hand,the working frequency of FPGA is much lower than that of the actual chips,so it adds delay registers in the interface and modifies the system software to evaluate the actual performance of the taped out chips,and the experiment result shows that the error is below 2%.