Design of an 8-Bit High-Speed Multiplier Embedded in MCU
JU Shui-rong · 2010
Design of an 8-bit multiplier for MCD was presented.In this circuit,partial products were generated by modified radix-4 Booth encoding,and then compressed with a modified compression array structure,which was optimized using sign extension reduction technique,and the final product was obtained with CLA array.The whole design was described in Verilog HDL at structure level,and synthesized based on SIMC's 0.18 μm standard cell library using DC of Synopsys.Results of the synthesis showed that the proposed multiplier had a delay of 5.31 ns and a system clock frequency up to 188 MHz.