A High-performance and Low-cost VLSI Implementation of the SHA-1 Hash Function
Zhang Zhang · Journal of Chinese Computer Systems · 2007
This paper presents an optimized architecture of a SHA-1 accelerator, based on Security Hash Algorithm. By improving the datapath and adopting the dynamic operand generation technology, the proposed design achieves the goal of high-performance and low-cost. Based on SMIC 0.25μm standard CMOS technology, the core circuit of this SHA-1 accelerator has about 16.8k gates. Under 86MHz system clock frequency, it achieves a throughput of about 1.07Gbps. The results shows that it is suitable for applications in PDA, mobile telephone, etc., which demands limited area.