Testing Time and Testing Power For a SOC Co-optimization
XU Dong-nin · Microcomputer Information · 2009
Convert the optimization problem of test time and test power of TAM bus to rectangle packing problem based on the flexible structure of the SoC bus test system. Propose the ‘time intervalspare bandwidth’ layout algorithm and dual-rectangle layout algorithm. By the Parthenon-genetic algorithm, convert the layout problem to rank which is translated to the corresponding layout diagram using the ‘time intervalspare bandwidth’ packing algorithm and dual-rectangle packing algorithm. The optimization problem of the test time and test power is resolved.