SAT-based Algorithm for Multiple Design Error Diagnosis
Pushan Tang · Microelectronics & Computer · 2007
A design error diagnosis algorithm for combinational circuits is presented.It can perform model-free logic error location by counting sat solutions with an all-solution SAT solver.Our algorithm offers two major advantages over existing methods.Firstly,we reduce the variables and the clauses using a novel diagnosis configuration.Secondly,a number of heuristics are proposed that keep the method memory and run-time efficient.