FPGA Implementation of Fast Floating-point Adder
LU Huan-zhang · Jisuanji gongcheng · 2005
Three commonly used Floating-point addition algorithms are discussed, and the LOP algorithm is implemented on VirtexII seriesFPGA. The implementing results show that the fast floating-point adder can be implemented on FPGA, the highest running frequency is 152MHzand the area cost is rational compare to the entire resources.