Hierarchical Clock Trees Design Analysis
Rao Quan-lin · Microelectronics & Computer · 2008
Hierarchical design,a bottom-up flow that is the main method used in complex IC.Also clock trees synthesis faces some untraceable difficulties along with hierarchical design.The paper analyzes some key points aimed at hierarchical clock trees synthesis in a complicated SoC.Practise indicats that convergence hierarchical clock trees can be achieved rapidly by the solution researched in this paper,also the efficiency.