Efficient Partial-parallel Architecture for Fast Modular Multiplication in GF(2~m)
Zhang Min-xuan · Jisuanji gongcheng · 2007
This paper analyzes the point multiplication in EC and educes the modular multiplication formula in GF(2m)for systolic implementation with partial-parallelism in MSB mode.Following the formula,it designs an efficient architecture of systolic array,studies the performance of the array element and compares with the performance in LSB mode.The simulation result proves that the partial-parallel architecture in MSB mode which supports flexible irreducible polynomials of GF(2m)can process modular multiplication efficiently with proper hardware cost,while the partial-parallel architecture which supports fixed irreducible polynomials can save the hardware cost and archive high performance at the same time.Both can improve the performance of ECC algorithms in GF(2m)efficiently.