Design of Computing Array Based on Extended Register and Network-on-Chip
Zhang Jia-ji · Jisuanji gongcheng · 2013
In order to improve the performance of multi-core processor,based on traditional hardware accelerator,this paper presents a novel computing array design scheme.The communication ports between the computing array and the processor are mapped in the address space of extended register file,which makes the computing array and the processor tightly coupled.The computing units are connected by Network-on-Chip(NoC) which enables the computing array be flexibly configured and highly shared by the multi-core processor.A 1 024-point Fast Fourier Transform(FFT) and an H.264 decoder are implemented on the experimental platform,and results show that the scheme can improve the performance and power consumption significantly compared to pure software solution.