Stability Condition of Adiabatic Memorial Unit and Adiabatic Synchronous Sequential Circuits in Three-phase-clock
Fang Zhen-xian · Journal of Circuits and Systems · 2003
Because of the importance of implementing adiabatic synchronous sequential circuits, the stability condition of adiabatic memorial circuits is presented in this paper. According to the stability condition, three-phase-clock is proved to be the minimum number of clocks satisfying circuit stabilization. On the basis of above theory, the adiabatic dynamic-static flip-flop is proposed, by which the adiabatic variable counter circuit with clear- data-feedback is designed. Finally, Computer simulation has shown that above flip-flop and adiabatic variable counter are stable with lower power consumption.