Studies on the Timing for Designing the High Speed Chip
Jin Lai · Microelectronics & Computer · 1999
The tolerance error of timing is very small in high speed chip design The quality of designs produced by design compiler depends on the accuracy of its wire estimation since the role of interconnect in determining the performance of high speed systems has been steadily increasing It is a need for more accurate and elaborate delay models, for the more accurate floorplan wiring estimates being back annotated in projecting the high speed chip This paper makes some investigations of these respects combining the design of BAP1024(Bit serial Array Process with 1024 process elements) chip