Architecture Optimization and Implementation of AES Algorithm
Haijin Chen · Microelectronics & Computer · 2007
This paper presents an architecture optimization for AES(Advanced Encryption Standard) algorithm,and a chip implementation using 0.6μm CMOS technology.Verilog HDL was used as the design entry,and the layout was designed by auto-synthesis tools.The designed chip supplies both the encryption and decryption modes and all the three kinds of AES key length.The observed data throughput rate was 49.2 Mbps for 128-bit keys,41.3Mbps for 192-bit keys,and 35.6 Mbps for 256-bit keys with a 20MHz clock.