ASIC Design of Channel Decoder in DRM Receiver
Yang Huazhong · Audio Engineering · 2007
The MSD technology is applied to the ASIC design of channel decoder of DRM receiver. As an IC design practice which reaches millionaired gates level, it has good reconfigurable and reusable characteristics. With 0.18um CMOS technology, the design can run at frequency up to 50 MHz, the area is 2 282 707.5 μm2, which is about 377 303 Nand (ND2LL) gate-count size.