Power analysis resistant AES crypto engine design for a network security co-processor
Yongsheng Yang · Journal of Tsinghua University(Science and Technology) · 2009
A low power masking technique is used to promote the power attack resistant of the AES(advanced encryption standard) crypto engine in high performance network security co-processors to achieve higher security against the side-channel attack technique,especially the power analysis attack.The data masking novel circuit design utilizing SRAM(static random access memory) with replication in other modules.The design uses data masking to generate random power to disguise the genuine power related to the secret data being analyzed.The attacker will then not be able to find the relationship between the power and the data.The power simulator PrimePower is used to collect power curves at each round when ciphering.Comparison shows that the original crypto engine can be successfully attacked within 1000 different power curves,while the masked crypto engines in the design can resist over 10000 curves.Thus,the security of the AES crypto engine is greatly improved by the design.Furthermore,the design is verified to be feasible by FPGA(field programmable gate array).