Design of BCH Encoder/Decoder for NAND Flash Controller
Haibin Shen · Jisuanji gongcheng · 2010
A new architecture of parallel BCH encoder and decoder applied in NAND Flash Controller is proposed.In order to obviously increase the throughput of decoder,pipeline operation and prefetch decoding in group operation are applied in the design.It takes 565 cycles to correct 8 bit random error after NAND Flash’s 2 KB page read operation,which is a quarter of the time cost by prefetch decode in page.