A pipelined loop array architecture
Zhigang Mao · Information technology newsletter · 2010
This paper describes a reconfigurable array architecture based on pipelined loop computing.That is,the array processor communicates with the main processor through the AMBA interface.The paper introduces the architecture of PLAA especially 2D-DCT arithmetic implementation.The simulation results show that PLAA can achieve seven times or much higher performance than general processor,and make a balance among complexity,performance and compatibility.