A Multi-frequency BIST IP Core with Scan Chain for Embedded Register File
Lin Hua · 2003
A multifrequency BIST design with scan chain presented here supports the 32 word by 32 bit, five po rt embedded register file which can perf orm simultaneous and independent reads a nd writes. We considered the special fau lt models for the complex structure of t he register file. A new algorithm named diagonal moving inversion and BIST circu it are created, which needs only N /2+2 N log 2 N operations but can achieve t he high fault coverage. This BIST design integrates functional test, dynamic par ameter capture and diagnosis together an d is flexible for all kinds of register files.