FPGA Implementation of High Throughput 2D-DCT
Jianfa Chen · Journal of Xiamen University · 2005
The discrete cosine transform(DCT) has been widely used in the implementation of low bit rate codes for video compression as an integral part of several international standards.In this paper,we present a high throughput 2D-DCT architecture with circuit designs in details,based on the algorithm of matrix row-column transposition.In order to improve the throughput performance,two technologies of pipeline structure and Double RAM Buffer are employed.At the end of this paper,the FPGA implementation and Verilog synthesis results are provided,which shows that the clock rate can achieve up to 140 MHz.It is well suited for the application in real time image and video compression system.