A Novel High-Speed Reconfigurable FIR Filter Based on CSD Coefficients
Guo Zhi-yong · Microelectronics & Computer · 2009
A novel architecture of high-speed and coarse-granularity reconfigurable FIR filter based on CSD coefficient is presented in this paper. The fabric adopts a new priority data select method to be reconfigurable and greatly decreases complexity of the processor. The max frequency of system is enhanced due to the delay of the critical path is minished by improving adder structure. Testing result show that area of the fabricated chip is 5.4mm×5.6mm while running at 131 MHz.