Integrated Design of DFT and on-Chip Debug System for SoC
Jinghe Wei · Electronics & Packaging · 2010
With the increasing complexity and chip scale of SoC, on-chip debug system and design-for-test (DFT) has become a more important parts of SoC and their similar structures are a waste of hardware resources. An structure for a SoC based on 32-bit RISC which integrates the test logic with the debugging logic is proposed. With using JTAG port, this structure can have an ability of debugging program, boundary scan test,logic scan test, SRAM BIST. It effectively decreased the chip area and reduced the chip pin increasing caused by the test logic.