Design for Testability of a 32-Bit MIPS Processor and Its Implementation
Ni Zhou, Fei Qiao, Tan Sisi, Li Chang, Yang Huazhong · 2010
A 32-bit MIPS processor was presented.To realize load balance and increase system efficiency,a custom five-stage pipeline structure was employed.Furthermore,data bypass and branch prediction based on history records were adopted to solve hazards of pipelined processor.In order to ensure reliability and testability,stage decomposition checking was used.Key signals of the pipeline stages were extracted as output signals.Meanwhile,multiple modes were proposed and reusing of pads were achieved to reduce chip area and number of pads.Post-layout simulation based on 0.18-μm CMOS technology indicated that the processor had a maximum frequency of 60 MHz.Having 135 k gates,the core circuit occupies a chip area of 1.15 mm×2.25 mm.With a total power consumption of 2.8 mW/MHz,the processor functions perfectly and switches properly between multiple modes.