Simulation of correlation power analysis against DES cryptographic chip
Ying Yan, Pla Information · Application of Electronic Technique · 2009
To study the ability of cryptographic chip′ s resistance to power analysis, this paper constructs a platform for power analysis. Combined DES algorithm, we do the correlation power analysis attack experiment based on this platform. With comparing the correlation coefficient between the power consumption of guessed partial key and the whole key, the correctness of the guessed partial key is confirmed by this method, the rest part of key can be achieved by this method. This method reveals the vulnerability of DES implementation without any countermeasure to CPA attacks.