One Way of Reducing the Hardware Resource Usage in FIR Design Using FPGA
Jun Chen · 2005
A new realizing structure of FIR digital filter is presented in the paper. The new structure greatly reduces the hardware usage of multiplier and ACC. First, discussion goes on two kinds of FIR hardware structure and thus shows the advantage of the new one presented here; later, with MATLAB and EDA simulation ,it is shown that as the digital filtering ability is concerned, there is no difference between the new structure and the traditional one .