Develop on NS Synchroniser Based on ISA Bus
Jun Tang · Ordnance Industry Automation · 2004
The ns synchronizer based on ISA bus was designed with programmable hardware delay, ns hardware circuit were connected with cascade connection of 10 pieces of MC100E195, and gate circuit was controlled by 17 bit addresses choosing bus through parallel interface 8255. It makes 8254 generate a vibratory pulse and this pulse triggers a gate arrays to generate a 20 ns grade delay pulse. 20 ns grade delay pulse was sent into MC100E195, delay range of 20 ns grade was gained. The operation of synchroniser hardware port was implemented with VC++, and multi-path delay synchronization signal was gained by setting parameter.