The CMOS circuit design of Gbps general Up/Down counter
Zeng Ze-cang · Journal of Xi'an University of Post and Telecommunications · 2008
In digital PLL,the up/down counter is the critical circuit of digital filter.This paper presented the principle of the general up/down counter,deduced the logic expressions of the circuit,and designed the circuit schematic of the 5 bits up/down counter which can be extended.The counter's functions were verified with the simulator NC-Verilog.It was implemented with CMOS circuit,and the transistor-level simulation was presented with the Cadence Spectre in the 0.18um CMOS technology.The highest frequency of this circuit is 1.25GHz.However,the highest frequency of the circuit which was synthesized from the synthesizable Verilog module in the same process is only 800MHz.