16×16 High-Speed Multiplier Design & Implementation
Mingyan Yu · Microelectronics & Computer · 2008
To get a high-performance multiplier,this paper presents a design,which generates partial products by modified Booth algorithm,compresses them using a Wallace tree structure and gets the final product with a CLA array.We optimize the compressor by means of reducing the amount of symbol padding,and reducing amount of padding 0 behind addends.Using the SMIC 0.18μm process,the synthesis result of this design by DC(Design Compiler)shows that the delay can be reduced to 4.62ns and the area is 23 837μm2.