VLSI implementation of a high-speed digital FIR filter
Honghui Deng · Journal of Hefei University of Technology · 2008
This paper introduces the implementation of a high-speed FIR filter.To meet the speed requirement of the filter,the multiplier-adder operation in the constant coefficient filter is achieved by using the constant multiplier-adder unit which is based on shift-add operation.This multiplier-adder unit is based on CSD coding and adopts both the 3-2 compressor and the Wallace tree.As a result,this new multiplier-adder unit has a significant advantage in speed in comparison with the traditional direct structure,and it occupies smaller area than the parallel multiplier-adder unit which is applied in the general multiplier.This filter has been applied in a high-speed DAC chip as an interpolation filter.