Research & FPGA Implementation of a High-Speed Fixed Point Multiplier
Jing Wei-ping · Microelectronics & Computer · 2005
This paper provides the design method of a high speed fixed point multiplier. It employs Modified Booth Arithmetic(MBA), Wallace-Tree, 4:2 Compressor, pseudo 4:2 compressor and the Suqare Root Carry-Select Adder. The multiplier has been realization using VerilogHDL, one 16bits multiplication can be performed in a clock. For verifying the performance of the multiplier, the multiplier has beed download into the VertexII-xc2v1000256-4, the frequency can reach 62.27MHz. 62.27 million times multiplication can be accomplished per second.