An On-Chip Wormhole Router Architecture with Dynamically Allocated Input-Queues
Yaming Yin · Dianzi xuebao · 2010
To reduce the performance lossing induced by head-of-line (HoL) blocking in traditional wormhole router,and eliminate the underutilizing of buffers when virtual-channel router is handling variable-length packets in Network-on-chip(NoC),in this paper,an on-chip wormhole router architecture with Dynamically Allocated Input-Queues(DAIQ) is proposed based on virtual channel technology.The proposed architecture allocates buffer resources dynamically to regulate the depth and number of virtual queues.Additional,a novel switch allocation mechanism-SRRM is proposed to keep granting flits from the same packet,and SRRM improves the latency and throughput of switch under high network load.The results of simulation and synthesis show that DAIQ router provides similar performance as a traditional on-chip virtual-channel router,but achieves about 50% savings in buffering resources and yields 30.18% savings of standard cells area and 38.4% savings of power under 0.13um CMOS process.