Technique for test structure reusing in SoC design
Yushan Li · Semiconductor Technology · 2004
To address the difficult problem of testing SoCs with IP structure, we can only use designFor Test methodology. For the reduction of the DFT work in SoC design process. This paper studied ona new test reuse technique based on the IEEE 1149.1 standard. The proposed test access logic can beused in variety of digital SoCs. And it also improved the fault coverage of the SoC. This technique hasbeen implemented in a computer vision SoC and the simulation result shows the efficiency of thereusable test structure.