An Architecture of a Low Miss-rate & Low Power TLB
Qixin Chen · 2004
In order to optimize performance, including speed and the usage of its memory, CPU usually hires a Translation Lookaside Buffer(TLB) to translate the virtual address into physical address. This paper presents a structure of a TLB that can be rendered by a 32-bit general CPU. The architecture of the TLB has two-level and two-page sizes. The fundamental memory unit of the TLB is a static RAM. Moreover, a further design methodology that can reduce the power consumption of TLB is also presented.