Design of a 67×67 bits Multiplier Employed Modified Booth4 Algorithm
Feng Liang · Dianzi qijian · 2007
It is proposed that a novel method for the design of 67×67 bits multiplier.First,a modified Booth4 algorithm is presented,which reduces the number of partial products,increases the compressing speed,and reduces the area by encoding the multipliers.After,research of optimizing and assigning to the carries generated by partial products and a 134 bits compensatory pattern,partial products are compressed by 4-2 and 3-2 compressors.At last,a modified 134 bits K-S adder is presented and employed to get the result. Using TSMC0.18 μm technology library and Synopsys's Design Compiler,Quautus4.2,compared with DesignWare's multiplier,the circuit of modified Booth4 algorithm is better in general.