On-chip debug design based on debug exception model for embedded processor
Kejun Wu · Journal of Zhejiang University(Engineering Science) · 2010
A general precise debug exception model based on pipeline was established with portability,which provides a strategy for on-chip debug by adding generation and processing mechanism of precise debug exceptions,such as debug interrupt,step,hardware/software breakpoints,etc.,in addition of a segment of off-chip debug memory and a fast transfer method through joint test action group(JTAG) port. The implementation of the proposed model on an embedded processor RISC32E shows that it meets the requirements of observability and controllability. The above description should not be taken as limiting the utilization of the model which is defined by the six-pipeline microprocessor. The model can be easily transplanted onto other microprocessors which have various modifications of pipeline. The proposed strategy has great efficiency of debugging in the case of comparison of some basic debugging operation overhead.