BIST Test Vector Generation for IDDT Testing
Jishun Kuang · Science Technology and Engineering · 2006
To test open-circuit failures in CMOS circuits usually needs to use test vector pairs. Built-in self-test(BIST)is used as an effective test technique and it can greatly reduce test overheads. A BIST test pattern generator for IDDT testing design. it can random generate a set of test pairs with 1~2 switches. Experiments show it can detect as more faults as possible with fewer test pairs.