VLSI Design of High-speed Reconfigurable Reed-Solomon Error-and-erasure Decoder
Jiang Hong-hui · Jisuanji gongcheng · 2011
Aiming at the problem that he research and application on reconfigurable error-and-erasure decoders remains limited.This paper presents a Very Large Scale Integration(VLSI) architecture for high-speed reconfigurable error-and-erasure Reed-Solomon(RS) decoder.In digital transmission procedure,RS codes are widely employed due to the excellent error/erasure correction capability.Based on the ultra-folded technology,the proposed architecture achieves not only high speed but also low hardware complexity.Through 0.18 μm technology and design complier tool,the results show that it is a competitive candidate in hardware complexity,throughput and reconfiguration.