VLSI programmable wavelet packet transform processor
Hongyi Chen · Journal of Tsinghua University(Science and Technology) · 1999
This paper investigates the hardware implementation of wavelet packet transforms. Because the existed hardware implementation schemes are often limited in application by being unsuitable for long support length wavelets and high level decomposition, this paper gives a hardware implementation scheme based on a two buffer structure which is programmable and universal. A universal wavelet packet transform chip is designed according to the scheme, and it is suitable for single chip implementation of being used as an engine unit in many application systems. The chip is simulated on FPGA with an ALTERA's FLEX10K chip by using SYNOPSYS' FPGA -COMPILER and ALTERA's MAX+PLUSII.