Hardware Implementation of Parallel MPEG-4 Video Variable Length Decoder
Lu Yu · 2004
This paper presents a parallel design of MPEG-4 Variable Length Decoder. The design uses barrel shifter and PLA-based parallel algorithm so that one variable length code can be decoded in every clock cycle. Some special approaches, such as pipelining, reconstructing variable length code tables and partitioning a long look-up table into several shorter ones, which facilitates parallelity, are introduced. These can reduce delays on critical path, thus raising working frequency. Real-time MPEG-4 ASP@L5 decoding is ensured by the foresaid methods.