Study on Efficient Encoding Structure of LDPC Codes Based on Matrix Partition
Quan Zhou · Microelectronics & Computer · 2007
Low-density parity-check(LDPC)codes have received intensive research for their capacity-approaching performance and highly parallelizable decoder architecture. However, the encoder and decoder hardware implementations are very difficult for the codes with larger block size. In this paper, considering the practical implementation of encoder and decoder, an efficient lower triangular parity matrix structure of LDPC codes based on matrix partition is presented in order to reduce the complexity for both encoding and decoding,which not only admits linear time encoding but also is suitable for partially parallel decoder implementation. Simulation results show that the LDPC codes constructed in this way are comparable to random ones in error-correcting performance.