Design of 32-bit multiplier with good speed performance
Zhen Zhang · Journal of Hefei University of Technology · 2004
A multiplier with good speed performance is a very important unit in the modern microprocessors because the cycle that a multiplier completes one multiplication operation determines the main frequency of the microprocessor. In summing of the last product in the traditional multiplier design, the array or iteration summing method is used, which is not suitable to the design of small or middle scale integration circuit. A 32-bit multiplier is presented in which many methods, such as Booth algorithm, 4-2 compressors, Wallace tree algorithm,and carry-lookahead adder, are applied, which results in high speed performance.