A low power deterministic test scheme based on random access scan structure
Zhang Minsheng · 2011
High density and large scale IC faces many problems during tests,such as huge amounts of test data,long test application time and high test power dissipation.A test scheme based on random access scan architecture for mixed-mode test was proposed.A pre-computed set of deterministic test cubes were embedded in test sequences generated on chip.The test process consists of two steps.The first step relied on a new type of test pattern generator called block-fixing folding(BFF) counter.The deterministic test cubes that detect most of the faults in the circuit under test were embedded into BFF test sequences.In BFF sequences,many blocks were fixed for increasing the efficiency of generating test patterns.The second step was to generate the remainder deterministic test patterns for hard-to-test faults by the bit-flipping approach.Experimental results on ISCAS-89 benchmark show that this scheme can not only reduce test data volume and test application time effectively,but also reduce test power consumption significantly.