A high level register allocation algorithm for minimizing BIST test resources
Chao Wang · Journal of Circuits and Systems · 2006
Considering testability during high level synthesis has several benefits,including reducing area overhead and performance degradation,improving test effectiveness and so on.In this paper,we present a register allocation algorithm based on pseudo-random testability metrics for minimizing Built-in Selftest(BIST) resources.Through a variety of synthesis benchmarks,experimental results show that the test resources reduction of up to 46.8% can be achieved by comparison with other BIST synthesis methods.