Design of low-power dynamic ternary CMOS D flip-flop
Wei Zhou · Journal of Zhejiang University(Science Edition) · 2007
Low power design is playing a more and more important role in VLSI nowadays.In this paper a low-power dynamic ternary CMOS D flip-flop was designed,which is based on the dynamic CMOS ternary inverter having full voltage swings without DC power dissipations and is combined with the structure of a Simple Ternary Differential Logic(STDL).This flip-flop has correct logic function as a dynamic D flip-flop,and has the distinct advantage of simple structure,small chip area,and simple two-phase clock.It was shown by the pspice simulation that it has faster speed and lower power,it can save nearly 35% power dissipation as comparing with binary dynamic TSPCL D flip-flop.