Research and Implementation of the ASIC Verification Prototype and Logic Partitioning Algorithms Based on FPGAs
Guangming Liu · Computer Engineering and Science · 2006
With the rapid growth of the ASIC design size and complexity,traditional verification approaches can hardly meet the emerging requirements.A new ASIC verification approach based on FPGAs can shorten the development cycle efficiently,implement verification more quickly and completely and satisfy the requirements of ASIC verification better.This paper discusses the reconfigurable interconnection structure of prototype systems,presents a partitioning algorithm,and gives the corresponding implementation.