80 Bit-Paralleled Three-Dimensional DCT Core Solution
Lei Dai · 2003
This paper proposes a new algorithm on motion pictu re compression and decompression using Three-dimensional Discrete Cosine Transfor m. The algorithm not only emphasizes reducing computation but also helpful with hardware implementation. Based on this approach, an 80 bit-parallelled 3D-DC T hardware is developed, which uses parallel multiplication to accelerate comput ation ,three-dimensinal transposition memory to remove the time consumption of transposition operation and temporary register to reduce the time of accessing i ntermediate values. FPGA simulations show that real time video 3D-DCT compressi on can be completed by using the hardware core.