A novel thread level dynamic scheduling model for heterogeneous MPcore based on configurable processor
Yuzhuo Fu · China Integrated Circuit · 2009
This paper proposes a novel thread level dynamic scheduling model. Through the relationships among processor cores, instruction sets (ISA) and threads, this model is able to dynamically assign a thread to a configurable processor core with partially instruction extension in heterogeneous multi-core architecture, which can speed up the performance with less area increasing than full instruction extension SMP architecture, and simplify the programming model.