A VLSI Architecture for Motion Estimation in H.264
Shibao Zheng · Tv Engineering · 2004
In this paper, a VLSI architecture for variable block size motion estimation (VBSME) in H.264 standard is proposed. A 1-D processing element (PE) array is adopted to implement the search algorithm for finding the best-matched block. For variable block size, the sum of absolute difference (SAD) is computed by reusing the results obtained from the computations of smaller sub-blocks. Whereas a conventional architecture can process only one motion vector, this architecture can process up to 41 motion vectors in a comparable number of clock cycles, with higher speed and less number of gates.