High-Speed Hardware Design and Implementation of AES Algorithm Based on 51 Core
Zeng Xiao-b · Electronic Science and Technology · 2016
An AES algorithm scheme is proposed for higher algorithm efficiency,lower complexity of key operations and better resistance of the key against brute-force attack and time attack. The AES principles and its on-chip implementation based on 8051 soft-core are presented with workflow system and hardware modules design given. The efficiency analysis and verification results on the hardware platform are provided. Simulation results show that the AES IP core by look-up table method has high efficiency,and offers support for algorithm engine in the So C decency password product development. A substantial increase in the efficiency of the algorithm is achieved at the mere cost of a small area of the exchange rate compared with conventional algorithms.