Improvement on FFT processors based on pipelined CORDIC architecture
Ao R · 2007
The pipelined CORDIC architecture is very suitable for FFT butterfly operation because of its high throughput and regularity, but it will consume lots of resources,this article presents an improved architecture of CORDIC pipeline,starting with the property that the FFT rotary factor is fixed but not arbitrary,and according to the mapping between the basic rotational angle of CORDIC and scale factor and the rule for transform among the scale factors.On the condition that the velocity of FFT butterfly operation maintains unchanged, the improved architecture not only will economize the resources but also can reduce the store room from 32 bits to 25 bits when the word-length of the system is 16 bits.