Design of a Low Power Architecture for Floating-Point Adders
Gao Hai · 2002
Floating point adder is an important block in IC datapaths Its performance and power consumptions have a great effect on the performance of processors and DSP's In this paper, several architectures for floating point adder are summarized and analyzed A low power triple datapath architecture is described in particular Finally, the practicability of floating point adder architecture has been analyzed